The introduction of the SAV process in the 20 nm technology node took advantage of the trench first process in addition to a trench hard mask to bound the via critical dimension (CD) at the edges of the metal hard mask where the via CD would overlap those metal edges. An SAV via process uses the “AND” of the metal hard mask opening and via pattern opening to form the final on wafer via shape that will be etched and then filled along with the metal trenches. An important benefit of the SAV process is that it eliminates the risk of an SAV via shorting to any adjacent metal lines in the direction of the SAV edges due to overlay, CD, and line edge roughness (LER) variability of the via. This is especially true as the pitch of the metal interconnects, polysilicon gates, and local interconnects become increasingly smaller. With the ever shrinking standard cell, pin accessibility becomes more limited, metal interconnect and local interconnect shapes become extremely congested, and the need for more aggressive and risky design rules becomes paramount.
Design rules are implemented to protect against a known limiting parameter and its failure mechanism, which can be calculated, measured, simulated, or modeled. The standard limiting parameters (SLPs) known to exist in past technologies include minimum polygon dimensions, printability of polygon shapes, inter and intra level polygon spacing, intersect area between two connecting shapes from adjacent levels, etc. For each SLP and respective failure criteria, design rule restrictions can be derived from ground rule calculations, 2-D litho simulations, Monte-Carlo intersect area modeling/simulations which are based on statistically predicted manufacturing environment process variables, such as CD tolerances, overlay tolerances, LER tolerances, and corner rounding estimates, etc.
In the 20 nm technology node, there have been many challenges trying to reach a competitive standard cell density. The usual SLPs have been pushed to the limits with the intent to enable a competitive standard cell design but have fallen short. Design analysis has shown that one design rule in particular is identified as a key blocking point in the development of a competitive standard cell height. This design rule restricts the via 0 (V0) distance to an M1 inner-vertex, which is based on a new concern that is unique to the SAV process, and which will be call a non-standard limiting parameter (NSLP) throughout this disclosure.
This NSLP is an acute angle created in the final via shape opening that will be etched and filled with metal. This acute angle can be a result of the interaction between the SAV pattern and the metal hard mask, forming a final top down shape that is the AND of both, as illustrated in FIG. 1A. Specifically, a drawn M1 shape 101 has a final hard mask CD shape 103, and a drawn V0 105 has a V0 retargeted litho shape 107. The intersection between the final hard mask CD shape 103 and the V0 retargeted litho shape 107 is the final V0 shape 109 (shown separately in FIG. 1B). The acute angle 111 in the final V0 shape 109 is the NSLP, or limiting parameter α.
The concern for integration teams is that the final V0 inner angle α, angle 111, created between V0 and the M1 hard mask, will be a yield concern with the failure criteria being the ability to properly fill the via. In particular, acute angles can create voids when depositing metal and eventually, if not immediately, create electrical opens.
A need therefore exists for methodology enabling designs with a reduced V0 distance to M1 inner vertex restriction.